This paper presents the evaluation of a non-blocking, decoupled/memory execution, multithreaded architecture known as the Scheduled Dataflow (SDF). Our research explores a simple, yet powerful execution paradigm that is based on non-blocking threads, and decoupling of memory accesses from execution pipeline. This paper compares the execution cycles required for programs on SDF with the execution cycles required by programs on Superscalar and VLIW architectures.
Kavi, K.M., Arul, J., Giorgi, R. (2001). Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications. In 14th Int.l Conf. on Parallel and Distributed Computing Systems ISCA-PDCS (pp.365-371). INTERNATIONAL SOCIETY COMPUTER S & THEIR APPLICATIONS (ISCA).
Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications
GIORGI R.
2001-01-01
Abstract
This paper presents the evaluation of a non-blocking, decoupled/memory execution, multithreaded architecture known as the Scheduled Dataflow (SDF). Our research explores a simple, yet powerful execution paradigm that is based on non-blocking threads, and decoupling of memory accesses from execution pipeline. This paper compares the execution cycles required for programs on SDF with the execution cycles required by programs on Superscalar and VLIW architectures.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
https://hdl.handle.net/11365/46879
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