Core Design and Scalability of Tiled SDF Architecture

Embedded systems are using more extensively multi-core chips to reach high performance goals. While current systems contain only a few cores, present trends and commercial/research roadmaps foresee that in a near future many cores will be integrated on the same chip to achieve the best tradeoff between power consumption and performance. At the same time, centralized designs are progressively abandoned in favour of more modular and scalable approaches that address explicitly wire delay problem and aim to exploit application parallelism. Such designs are often referred as tiled architectures. Here we present our idea how the tiled paradigm can be applied on the SDF architecture.