TERAFLUX: Ideas for the Future Many-Cores

Recent Silicon advances promise to keep Moore s Forecast true for at least this decade. In numbers, one TERA (10^12) transistors in a single chip or package will be available, posing three major challanges for future computing systems: i) how to efficiently program these systems? ii) which architecture would lead to a managable complexity? iii) how do we keep the system reliable? The TERAFLUX project ( http://teraflux.eu - with a total cost of about 7.5 M-Euro) allows 10 Academic and Industrial partners to join forces in order to propose a holistic solution able to address the three above challanges. Many proposals for future many-core system are gaining attention nowadays: CUDA based systems contain already 512 cores per chip, while x86 multi-core processors arrived already to 12 cores. TERAFLUX leverages Dataflow Parallelism to reach power efficiency, reliability, efficient parallel programmability, scalability, data bandwidth. Dataflow is exploited both at task level and inside the threads, to offload accelerated codes, to localize the computation, for managing the fault information with appropriate protocols, to easily migrate code to the available/ working components and to respect the power/performance/temperature/reliability envelope, to produce a more predictable behavior, to efficiently handle the parallelism and have an easy and powerful execution model. A special challange is the evaluation of such system comprising a target of at least 1000 cores. Our simulation infrastructure relies on the COTSon simulator provided by HP-Labs (TERAFLUX partner). One more contribution of this project is to provide an updated COTSon-based TERAFLUX simulator as an Open-Source project.