Power modeling of precharged address bus and application to multi-bit DPA attacks to DES algorithm

In this communication, a model of the precharged bus power consumption in digital VLSI circuits is developed. This model is used to analytically evaluate the result of a multi-bit Differential Power Attack (DPA) to the address bus of cryptographic ICs running the DES algorithm. This attack to the address bus is based on the observation of its power consumption, and is well known to be a major threat to the security of the confidential information stored or processed by SmartCards. The results allow to achieve a quantitative model of the DPA attack effectiveness, and is useful as a theoretical basis to understand the trade-offs involved in DPA attacks. This deeper understanding is useful to identify the cases where a SmartCard under attack is weaker with respect to DPA attacks, i.e. when the power consumption reveals the maximum amount of information. Cycle-accurate simulations on DES encryption algorithm running on a MIPS32® architecture are used to validate the model and the underlying assumptions.