Analysis of the Impact of Random Process Variations in CMOS Tapered Buffers

In this paper. The effect of intradie process variations oy the delay of tapered buffers designed in static CMOS logic style is analyzed in depth. An analytical delay model accounting for the dependency of variations on transistor sizing, load and input capacitance requirement is derived for the single stage. Then, this model is extended to the case of N-stage tapered buffers. The closed-form delay expressions includin. The contribution of intradie variations permit to gain an insight int. The impact of process variations oy the performance of tapered buffers. Monte Carlo simulations on a 90-nm technology including layout parasitica are performed to validat. The analysis. Results are shown to agree well wit. The expressions derived, thereby confirmin. The validity oy the underlying assumptions, as well at the suitability oy the proposed models for design purposes. © 2009 IEEE.