Optimum Clock Slope for Flip-Flops within a Clock Domain: Analysis and a Case Study

In this paper. The impact of clock slope specification oy the energy consumption of a clock domain is analyzed. Results show that the clock slope requirement can be relaxed at the cost of a very small speed penalty and energy increase i. The flip-flops (FFs). O. The other hand, relaxin. The clock slope specification allows for downsizin. The local buffers drivin. The FFs that belong to the same clock domain. Froy the energy point of view, an optimum clock slope is found that leads to energy savings of 30 ÷ 40 % compared to the usually adopted clock slopes. The effectiveness oy the clock slope optimization, includin. The impact on local skew/jitter sources, is discussed for the typical case of Master-Slave FFs by resorting to simulations on a 65-nm CMOS technology. ©2009 IEEE.