In this paper, a comparison of the most representative flip-flop (FF) topologies in a 65-nm CMOS technology is carried out. For the first time in the literature, local wires capacitances are included in the transistor-level design loop, allowing to reach the actual optimum designs, given the huge impact that local interconnects have on both energy and delay (E-D) of FFs. The investigation permits to identify the most suitable FFs for low-energy and energy-efficient circuits in nanometer technologies.

Alioto, M.B.C., E., C., G., P. (2010). Physical Design Aware Selection of Energy-Efficient and Low-Energy Nanometer Flip-Flops. In Proc. of ICM 2010 (pp.60-63). New York : IEEE [10.1109/ICM.2010.5696206].

Physical Design Aware Selection of Energy-Efficient and Low-Energy Nanometer Flip-Flops

ALIOTO, MASSIMO BRUNO CRIS;
2010-01-01

Abstract

In this paper, a comparison of the most representative flip-flop (FF) topologies in a 65-nm CMOS technology is carried out. For the first time in the literature, local wires capacitances are included in the transistor-level design loop, allowing to reach the actual optimum designs, given the huge impact that local interconnects have on both energy and delay (E-D) of FFs. The investigation permits to identify the most suitable FFs for low-energy and energy-efficient circuits in nanometer technologies.
2010
9781612841496
978-1-61284-151-9
Alioto, M.B.C., E., C., G., P. (2010). Physical Design Aware Selection of Energy-Efficient and Low-Energy Nanometer Flip-Flops. In Proc. of ICM 2010 (pp.60-63). New York : IEEE [10.1109/ICM.2010.5696206].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11365/36363
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