Analysis and design of MCML gates with hysteresis

In this paper, hysteresis is exploited to improve the performance of positive feedback source coupled logic circuits, which are a modification of the traditional MOS current-mode logic (MCML) (Alioto, 2004). To understand the effect of hysteresis on the DC characteristics, a model of the noise margin is analytically derived. This model shows that hysteresis improves the noise margin, whose increase is traded-off to reduce the logic swing, which in turn can have a beneficial impact on the speed performance. Practical cases where hysteresis is advantageous are identified, and a comparison with PFSCL gates without hysteresis is carried out. Analysis shows that in such cases hysteresis significantly improves the speed performance and the power efficiency of PFSCL gates, which is a critical aspect in this kind of logic. Simulation results are presented based on a 0.18-mum CMOS process