In the embedded domain, the gap between memory and processor performance and the increase in application complexity need to be supported without wasting precious system resources: die size, power, etc. For these reasons, effective exploitation of small and simple cache memories is of the utmost importance. However, programs running on such caches can experience serious inefficiencies due to cache conflicts. We present a new Cache-Aware Code Allocation Technique (CAT), which transforms the structure of programs so that their behavior toward memory can meet the locality features the cache is able to exploit. The proposed approach uses detailed information of program execution to place program areas into memory and employs the new idea of “look-forward estimation” that helps to seek better global layouts during the placement of each area. CAT-optimized programs outperform the original ones achieving the same miss rate on two times, and sometimes four times, smaller caches. Moreover, CAT improves the instruction miss rate by more than 40% if compared to the best procedure-reordering algorithm. CAT performances derive from the increased number of cache lines that support the execution of optimized applications and from a more balanced load on them.
Bartolini, S., & Prete, C.A. (2005). Optimizing instruction cache performance of embedded systems. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 4(4), 934-965.
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|Titolo:||Optimizing instruction cache performance of embedded systems|
|Citazione:||Bartolini, S., & Prete, C.A. (2005). Optimizing instruction cache performance of embedded systems. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 4(4), 934-965.|
|Appare nelle tipologie:||1.1 Articolo in rivista|
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