Exploiting Chaotic Dynamics For A-D Converter Testing

In this paper we discuss the possible use of chaotic signals for testing Analog-to-Digital Converters (ADCs), with particular reference to the well-known Code Density Test (CDT, also called Histogram Test). In detail, we discuss the implementation of a chaos-based discrete-time noise generator circuit, providing the theoretical analysis of its statistical characterization. The implementation of the chaos-based device is discussed with reference to a generic hardware architecture, taking into account the nonidealities introduced by the presence of noise and the variability of the circuit parameters. Based on this device, we propose a method for generating noisy samples that are distributed, over a target subinterval of the circuit output range, according to a probability density function (pdf) that can be made arbitrarily close to the ideal uniform pdf, in exchange for an acceptable reduction of the uniform-distributed samples generation rate. Theoretical results, also supported by two experiments, confirm the reliability of the proposed solution, showing that chaotic systems can represent an alternative with respect to traditional methods for the generation of signals to be used in the Code Density Test of ADCs.