In this work an original CMOS implementation of a discrete-time deterministic-chaos algorithm for random bit generation is presented. The proposed circuit topology prevents the degradation of the generated-sequence statistical properties that can be caused by several factors, including the parameter spreading of the technological processes. Experimental results show that, with a final rate of 3 Mbit/s, the circuit is compliant with the most recent security requirements for cryptographic modules issued by the American National Institute of Standards and Technologies.

Fort, A., Cortigiani, F., Rocchi, S., Vignoli, V. (2003). Very high-speed true random noise generator. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 34(2), 97-105 [10.1023/A:1021976717094].

Very high-speed true random noise generator.

FORT, ADA;ROCCHI, SANTINA;VIGNOLI, VALERIO
2003-01-01

Abstract

In this work an original CMOS implementation of a discrete-time deterministic-chaos algorithm for random bit generation is presented. The proposed circuit topology prevents the degradation of the generated-sequence statistical properties that can be caused by several factors, including the parameter spreading of the technological processes. Experimental results show that, with a final rate of 3 Mbit/s, the circuit is compliant with the most recent security requirements for cryptographic modules issued by the American National Institute of Standards and Technologies.
2003
Fort, A., Cortigiani, F., Rocchi, S., Vignoli, V. (2003). Very high-speed true random noise generator. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 34(2), 97-105 [10.1023/A:1021976717094].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11365/19350
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