In this paper, an analytical delay model of Source-Coupled Logic (SCL) gates is proposed. In particular, the multiplexer, the XOR and the D-latch gates are considered. The method starts from a linearization of SCL gates, and analysis of the equivalent circuit obtained is simplified by introducing the dominant-pole approximation. The delay expression obtained is quite simple and each term has an evident circuit meaning, hence it is useful to design. The model was validated by extensive comparison with Spectre simulations by using a 0.35-µm CMOS technology. Results show that the predicted delay values agree well with simulated results. © Springer-Verlag Berlin Heidelberg 2002.
Alioto, M., Palumbo, G. (2002). Modeling Propagation Delay of MUX, XOR and D-Latch Source-Coupled Logic Gates. In PATMOS'02 (pp.429-437). Springer [10.1007/3-540-45716-x_43].
Modeling Propagation Delay of MUX, XOR and D-Latch Source-Coupled Logic Gates
ALIOTO M.;
2002-01-01
Abstract
In this paper, an analytical delay model of Source-Coupled Logic (SCL) gates is proposed. In particular, the multiplexer, the XOR and the D-latch gates are considered. The method starts from a linearization of SCL gates, and analysis of the equivalent circuit obtained is simplified by introducing the dominant-pole approximation. The delay expression obtained is quite simple and each term has an evident circuit meaning, hence it is useful to design. The model was validated by extensive comparison with Spectre simulations by using a 0.35-µm CMOS technology. Results show that the predicted delay values agree well with simulated results. © Springer-Verlag Berlin Heidelberg 2002.
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https://hdl.handle.net/11365/17325
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