Nanometer MCML Gates: Models and Design Considerations

In this paper, analytical models of the static and dynamic behavior of MOS Current-Mode Logic (MCML) with a resistive load are discussed. These models account for Deep-Submicron (DSM) effects which affect the operation of this CMOS logic style in the nanometer regime. In particular, a noise margin model is derived by resorting to the Alpha-Power law, and comparison with the long-channel expression allows for clearly understanding the impact of DSM effects. The dynamic behavior is also analyzed by accurately modeling the resistive load, i.e. accounting for its capacitive parasitics, which are shown to give an important contribution in low-power designs. Analytical results and considerations are validated by means of Spectre simulations on a 90-nm CMOS technology.