In this communication adiabatic and conventional gates with a different Can-in are modeled and analytically compared. The comparison is carried out assuming both an assigned power supply and setting it to minimize power consumption. The analysis leads to simple expressions, which allow to understand how the power advantage of adiabatic logic changes by increasing the fan-in of the implemented gate, The analytical results were validated by means of Spice simulations using a 0.8 mum CMOS technology.
Alioto, M., Palumbo, G. (2000). Modeling of Power Consumption of Adiabatic Gates versus Fan In and Comparison with Conventional Gates. In PATMOS 2000 (pp.265-275). Berlin : SPRINGER-VERLAG BERLIN [10.1007/3-540-45373-3_28].
Modeling of Power Consumption of Adiabatic Gates versus Fan In and Comparison with Conventional Gates
ALIOTO M.;
2000-01-01
Abstract
In this communication adiabatic and conventional gates with a different Can-in are modeled and analytically compared. The comparison is carried out assuming both an assigned power supply and setting it to minimize power consumption. The analysis leads to simple expressions, which allow to understand how the power advantage of adiabatic logic changes by increasing the fan-in of the implemented gate, The analytical results were validated by means of Spice simulations using a 0.8 mum CMOS technology.
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https://hdl.handle.net/11365/17318
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