In this paper, the modeling of the output transition time in Deep-Submicron (DSM) CMOS gates is discussed. In particular, the analysis starts from a previously proposed analytical model valid only for ramp inputs [1]-[2]. This model is then improved by introducing two semi-empirical coefficients which have to be tuned by means of two SPICE simulations. Since an exponential input is more and more frequent in current DSM CMOS technologies, the model is extended to this kind of input waveform. Results are validated with simulations on a 0.18-mu m CMOS technology. The output transition time model is found to be in good agreement with SPICE simulations, with an average error of only 5%.
Alioto, M.B.C., G., P., M., P. (2006). Efficient Output Transition Time Modeling in CMOS Gates with Ramp/Exponential Inputs. In Proc. of ISCAS 2006 (pp.5127-5130). New York : IEEE.
Efficient Output Transition Time Modeling in CMOS Gates with Ramp/Exponential Inputs
ALIOTO, MASSIMO BRUNO CRIS;
2006-01-01
Abstract
In this paper, the modeling of the output transition time in Deep-Submicron (DSM) CMOS gates is discussed. In particular, the analysis starts from a previously proposed analytical model valid only for ramp inputs [1]-[2]. This model is then improved by introducing two semi-empirical coefficients which have to be tuned by means of two SPICE simulations. Since an exponential input is more and more frequent in current DSM CMOS technologies, the model is extended to this kind of input waveform. Results are validated with simulations on a 0.18-mu m CMOS technology. The output transition time model is found to be in good agreement with SPICE simulations, with an average error of only 5%.
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https://hdl.handle.net/11365/17282
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