We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O (100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system. © 2007 Elsevier B.V. All rights reserved.
Belletti, F., Cotallo, M., Cruz, A., Fernandez, L.A., Gordillo, A., Maiorano, A., et al. (2008). Simulating spin systems on IANUS, an FPGA-based computer. COMPUTER PHYSICS COMMUNICATIONS, 178(3), 208-216 [10.1016/j.cpc.2007.09.006].
Simulating spin systems on IANUS, an FPGA-based computer
Andrea Maiorano;
2008-01-01
Abstract
We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O (100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system. © 2007 Elsevier B.V. All rights reserved.File | Dimensione | Formato | |
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https://hdl.handle.net/11365/1126640