Sfoglia per Autore
FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm
2025-01-01 Giorgi, Roberto
HashGrid: An optimized architecture for accelerating graph computing on FPGAs
2025-01-01 Sahebi, Amin; Procaccini, Marco; Giorgi, Roberto
A Survey on Real-Time Object Detection on FPGAs
2025-01-01 Hozhabr, SEYED HANI; Giorgi, Roberto
Real-time Object Detection on FPGA-based Heterogeneous MPSoCs: A Preliminary Analysis of the Execution Bottlenecks
2025-01-01 Hozhabr, S. H.; Giorgi, R.
A survey of graph convolutional networks (GCNs) in FPGA-based accelerators
2024-01-01 Procaccini, Marco; Sahebi, Amin; Giorgi, Roberto
DF-Threads: A Scalable and Efficient Execution Paradigm for Edge Computing and HPC
2024-01-01 Giorgi, Roberto
Accelerating Large-Scale Graph Processing with FPGAs Lesson Learned and Future Directions
2024-01-01 Procaccini, Marco; Sahebi, Amin; Barbone, Marco; Luk, Wayne; Gaydadjiev, Georgi; Giorgi, Roberto
Distributed large-scale graph processing on FPGAs
2023-01-01 Sahebi, A.; Barbone, M.; Procaccini, M.; Luk, W.; Gaydadjiev, G.; Giorgi, R.
WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool
2022-01-01 Mariotti, G.; Giorgi, R.
The AXIOM Project: IoT on Heterogeneous Embedded Platforms
2021-01-01 Filgueras, Antonio; Vidal, Miquel; Mateu, Marc; Jimenez-Gonzalez, Daniel; Alvarez, Carlos; Martorell, Xavier; Ayguade', Eduard; Theodoropoulos, Dimitrios; Pnevmatikatos, Dionisios; Gai, Paolo; Garzarella, Stefano; Oro, David; Hernando, Javier; Bettin, Nicola; Pomella, Alberto; Procaccini, Marco; Giorgi, Roberto
DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model
2021-01-01 Giorgi, R.; Procaccini, M.; Sahebi, A.
The Italian research on HPC key technologies across EuroHPC
2021-01-01 Aldinucci, M.; Agosta, G.; Andreini, A.; Ardagna, C. A.; Bartolini, A.; Cilardo, A.; Cosenza, B.; Danelutto, M.; Esposito, R.; Fornaciari, W.; Giorgi, R.; Lengani, D.; Montella, R.; Olivieri, M.; Saponara, S.; Simoni, D.; Torquati, M.
A Dynamic Load Balancer for a Cluster of FPGA SoCs
2020-01-01 KHALILI MAYBODI, Farnam; Giorgi, Roberto
An Extended Tracing System for the COTSon Simulator
2020-01-01 Procaccini, Marco; Giorgi, Roberto
WebRISC-V: A RISC-V Educational Simulator featuring RV64IM, Pipeline and Web-Based UI
2020-01-01 Giorgi, Roberto; Mariotti, Gianfranco
X86_64 vs Aarch64 Performance Validation with COTSon
2019-01-01 Giorgi, Roberto; Procaccini, Marco
A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface
2019-01-01 KHALILI MAYBODI, Farnam; Giorgi, Roberto
AXIOM: a scalable, efficient and reconfigurable embedded platform
2019-01-01 Giorgi, R.; Procaccini, M.; Khalili, F.
Embedded Face Analysis for Smart Videosurveillance
2019-01-01 Giorgi, R.; Oro, D.; Ermini, S.; Montefoschi, F.; Rizzo, A.
Bridging a Data-Flow Execution Model to a Lightweight Programming Model
2019-01-01 Giorgi, R.; Procaccini, M.
| Titolo | Data di pubblicazione | Autore(i) | File | Abstract |
|---|---|---|---|---|
| FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm | 1-gen-2025 | Giorgi, Roberto | - | |
| HashGrid: An optimized architecture for accelerating graph computing on FPGAs | 1-gen-2025 | Sahebi, Amin; Procaccini, Marco; Giorgi, Roberto | - | |
| A Survey on Real-Time Object Detection on FPGAs | 1-gen-2025 | Hozhabr, SEYED HANI; Giorgi, Roberto | - | |
| Real-time Object Detection on FPGA-based Heterogeneous MPSoCs: A Preliminary Analysis of the Execution Bottlenecks | 1-gen-2025 | Hozhabr, S. H.; Giorgi, R. | - | |
| A survey of graph convolutional networks (GCNs) in FPGA-based accelerators | 1-gen-2024 | Procaccini, Marco; Sahebi, Amin; Giorgi, Roberto | - | |
| DF-Threads: A Scalable and Efficient Execution Paradigm for Edge Computing and HPC | 1-gen-2024 | Giorgi, Roberto | - | |
| Accelerating Large-Scale Graph Processing with FPGAs Lesson Learned and Future Directions | 1-gen-2024 | Procaccini, Marco; Sahebi, Amin; Barbone, Marco; Luk, Wayne; Gaydadjiev, Georgi; Giorgi, Roberto | - | |
| Distributed large-scale graph processing on FPGAs | 1-gen-2023 | Sahebi, A.; Barbone, M.; Procaccini, M.; Luk, W.; Gaydadjiev, G.; Giorgi, R. | - | |
| WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool | 1-gen-2022 | Mariotti, G.; Giorgi, R. | - | |
| The AXIOM Project: IoT on Heterogeneous Embedded Platforms | 1-gen-2021 | Filgueras, Antonio; Vidal, Miquel; Mateu, Marc; Jimenez-Gonzalez, Daniel; Alvarez, Carlos; Martorell, Xavier; Ayguade', Eduard; Theodoropoulos, Dimitrios; Pnevmatikatos, Dionisios; Gai, Paolo; Garzarella, Stefano; Oro, David; Hernando, Javier; Bettin, Nicola; Pomella, Alberto; Procaccini, Marco; Giorgi, Roberto | - | |
| DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model | 1-gen-2021 | Giorgi, R.; Procaccini, M.; Sahebi, A. | - | |
| The Italian research on HPC key technologies across EuroHPC | 1-gen-2021 | Aldinucci, M.; Agosta, G.; Andreini, A.; Ardagna, C. A.; Bartolini, A.; Cilardo, A.; Cosenza, B.; Danelutto, M.; Esposito, R.; Fornaciari, W.; Giorgi, R.; Lengani, D.; Montella, R.; Olivieri, M.; Saponara, S.; Simoni, D.; Torquati, M. | - | |
| A Dynamic Load Balancer for a Cluster of FPGA SoCs | 1-gen-2020 | KHALILI MAYBODI, Farnam; Giorgi, Roberto | - | |
| An Extended Tracing System for the COTSon Simulator | 1-gen-2020 | Procaccini, Marco; Giorgi, Roberto | - | |
| WebRISC-V: A RISC-V Educational Simulator featuring RV64IM, Pipeline and Web-Based UI | 1-gen-2020 | Giorgi, Roberto; Mariotti, Gianfranco | - | |
| X86_64 vs Aarch64 Performance Validation with COTSon | 1-gen-2019 | Giorgi, Roberto; Procaccini, Marco | - | |
| A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface | 1-gen-2019 | KHALILI MAYBODI, Farnam; Giorgi, Roberto | - | |
| AXIOM: a scalable, efficient and reconfigurable embedded platform | 1-gen-2019 | Giorgi, R.; Procaccini, M.; Khalili, F. | - | |
| Embedded Face Analysis for Smart Videosurveillance | 1-gen-2019 | Giorgi, R.; Oro, D.; Ermini, S.; Montefoschi, F.; Rizzo, A. | - | |
| Bridging a Data-Flow Execution Model to a Lightweight Programming Model | 1-gen-2019 | Giorgi, R.; Procaccini, M. | - |
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