The proceedings contain 6 papers. The topics discussed include: analyzing block locality in Morton-order and Morton-hybrid matrices; investigating cache energy and latency break-even points in high performance processors; evaluating instruction cache vulnerability to transient errors; a simple speculative load control mechanism for energy saving; data prefetching in a cache hierarchy with high bandwidth and capacity; and an LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches.
Bartolini, S., Foglia, P., Giorgi, R., Prete, C.A. (a cura di). (2006). Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures. NEW YORK, NY : ACM Press [10.1145/1166133].
Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures
BARTOLINI, S.;GIORGI, R.;
2006-01-01
Abstract
The proceedings contain 6 papers. The topics discussed include: analyzing block locality in Morton-order and Morton-hybrid matrices; investigating cache energy and latency break-even points in high performance processors; evaluating instruction cache vulnerability to transient errors; a simple speculative load control mechanism for energy saving; data prefetching in a cache hierarchy with high bandwidth and capacity; and an LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches.
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https://hdl.handle.net/11365/46869
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