Co-tuning of a Hybrid Electronic-optical Network for Reducing Energy Consumption in Embedded CMPs

Nanophotonic is a promising solution for on-chip intercon- nection due to its intrinsic low-latency and especially low- power features, desirable especially in future chip multipro- cessors (CMPs) for rich client devices. In this paper we address the co-design of the parameters of a hybrid on-chip network featuring a traditional 2D mesh and a simple pho- tonic helper ring aimed to improve performance and reduce energy consumption. As all the CMP traffic cannot be sus- tained in the considered simple optical interconnection with- out saturating the available bandwidth, and thus inducing performance and energy degradations, we identify the subset of coherency messages that are most worth to be accelerated through the low-energy optical path. We investigate the management/arbitration strategies for the physically shared photonic path as they are crucial for reaching an effective exploitation of optical bandwidth ac- cording to their overhead and parallelism achieved in mes- sage transmission. Our results on multithreaded bench- marks, highlight that a careful selection of the most latency- critical messages to be routed on the photonic-path along with a Multiple-Writers-Single-Reader access scheme allows execution time and energy improvements up to 19% and 5%, respectively, for the 8-core setup and up to 16% and 13% for the 16-core configuration. Furthermore, we show that the most aggressive ring access schemes allow the adoption of a four times slower electronic NoC that trades the achieved average speedup margin to obtain 70% overall energy savings, which is extremely im- portant in energy constrained devices. Copyright 2013 ACM.