In this work an original CMOS implementation of a discrete-time deterministic-chaos algorithm for random number generation is presented. The proposed circuit topology prevents the degradation of the generated-sequence statistical properties that can be caused by several factors, including the parameter spreading of the technological processes. Experimental results show that the circuit can issue delta-correlated 1-bit digital sequences with a generation maximum frequency above 12 MHz
Cortigiani, F., Petri, C., Rocchi, S., Vignoli, V. (2000). Very high-speed true random noise generator. In Proceedings of the 7th IEEE Electronics, Circuits and Systems International Conference (ICECS 2000) (pp.120-123). IEEE [10.1109/ICECS.2000.911499].
Very high-speed true random noise generator
ROCCHI S.;VIGNOLI V.
2000-01-01
Abstract
In this work an original CMOS implementation of a discrete-time deterministic-chaos algorithm for random number generation is presented. The proposed circuit topology prevents the degradation of the generated-sequence statistical properties that can be caused by several factors, including the parameter spreading of the technological processes. Experimental results show that the circuit can issue delta-correlated 1-bit digital sequences with a generation maximum frequency above 12 MHz
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https://hdl.handle.net/11365/34943
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