Silicon Physical Unclonable Functions (PUFs) are innovative circuit primitives whose digital output strictly depend on the manufacture random physical variations introduced during the fabrication process of integrated circuits. In this paper we discuss the statistical characterization of a simple PUF module based on ring oscillators to implement challenge-response FPGA authentication. Differently from other approaches, in our proposed solution the challenge bits play a role in changing the time dynamics involved in the chip response measurement. The experimental results show that considering proper values for the challenge bits the repeatability error rate is smaller than 5% at given chip temperature and supply voltage, obtaining a PUF module working with 4 challenge bits whereas exhibiting an high sensitivity to the manufacture random physical variations. The obtained results are comparable to that ones presented for other solutions, with a limited consumption of hardware resources.
Addabbo, T., Fort, A., Mugnaini, M., Rocchi, S., Vignoli, V. (2012). Statistical characterization of a FPGA PUF module based on ring oscillators. In Proceedings of the 2012 IEEE International Instrumentation and Measurement Technology Conference (2012 I2MTC) (pp.1770-1773). New York : IEEE [10.1109/I2MTC.2012.6229468].
Statistical characterization of a FPGA PUF module based on ring oscillators
ADDABBO, TOMMASO;FORT, ADA;MUGNAINI, MARCO;ROCCHI, SANTINA;VIGNOLI, VALERIO
2012-01-01
Abstract
Silicon Physical Unclonable Functions (PUFs) are innovative circuit primitives whose digital output strictly depend on the manufacture random physical variations introduced during the fabrication process of integrated circuits. In this paper we discuss the statistical characterization of a simple PUF module based on ring oscillators to implement challenge-response FPGA authentication. Differently from other approaches, in our proposed solution the challenge bits play a role in changing the time dynamics involved in the chip response measurement. The experimental results show that considering proper values for the challenge bits the repeatability error rate is smaller than 5% at given chip temperature and supply voltage, obtaining a PUF module working with 4 challenge bits whereas exhibiting an high sensitivity to the manufacture random physical variations. The obtained results are comparable to that ones presented for other solutions, with a limited consumption of hardware resources.File | Dimensione | Formato | |
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https://hdl.handle.net/11365/32156
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