Fetching instructions from a set-associative cache in an embedded processor can consume a large amount of energy due to the tag checks performed. Recent proposals to address this issue involve predicting or memoizing the correct way to access. However, they also require significant hardware storage which negates much of the energy saving. This paper proposes way-placement to save instruction cache energy. The compiler places the most frequently executed instructions at the start of the binary and at runtime these are mapped to explicit ways within the cache. We compare with a state-of-the-art hardware technique and show that our scheme saves almost 50% of the instruction cache energy compared to 32% for the hardware approach. We report results on a variety of cache sizes and associativities, achieving 59% instruction cache energy savings and an ED product of 0.80 in the best configuration with negligible hardware overhead and no ISA changes.
|Titolo:||Instruction cache energy saving through compiler way-placement|
|Citazione:||Jones, T., Bartolini, S., Cavazos, J., DE BUS, B., & O'Boyle, M. (2008). Instruction cache energy saving through compiler way-placement. In Design, Automation and Test in Europe (DATE), 2008 (pp.1196-1201). IEEE.|
|Appare nelle tipologie:||4.1 Contributo in Atti di convegno|
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