Integration of RISC-V Page Table Walk in gem5 SE Mode

gem5 is a popular architectural simulator, for both academic and industrial researchers. It can be used in two configurations: Full System mode and Syscall Emulation mode. The former requires running a real kernel to achieve realistic results, at the cost of increased user effort. In contrast, the latter emulates operating system functionalities, which improves usability but is more prone to producing less accurate results. Due to the absence of a genuine kernel in Syscall Emulation mode, the simulator model of virtual address translation remains inaccurate. In the current gem5 version (v23.0.1.0), the address translation is performed through the lookup of a flat structure that stores all the virtual-to-physical mappings. However, this approach does not reflect the behaviour of a real multi-level page table, lacking the additional latency associated with page walks. In this paper, we present our implementation of the page walk functionality in Syscall Emulation mode for the RISC-V ISA. We show how our page walker affects the performance of simulated benchmarks and also its sensitivity on the TLB size. Furthermore, we make our work publicly available, inviting fellow researchers to utilize and build upon the model to suit their specific requirements.