Spin-glasses have become one of the most computing-demanding problems of the last 50 years in Statistical Physics. These extremely slow systems represent a clear example of an easy-to-describe but hard-to-simulate numerical problem. We have developed an FPGAs architecture, called Janus, able to exploit the simplicity of the problem by an extensive parallelization of the computing units. In this work we describe the architecture after motivating the problem. We give the performance figures compared with other more usual architectures. We have obtained a clear advantage in terms of computing power which produced several top results in the field. In addition, we describe the current development of the next generation of the infrastructure: Janus II. © IFAC.

M., B.J., R. A., B.N., A., C., L. A., F., J. M., G.N., A., G.G., et al. (2013). The Janus project: Boosting spin-glass simulations using FPGAs. In Programmable Devices and Embedded Systems (pp.227-232). IFAC Secretariat [10.3182/20130925-3-cz-3023.00039].

The Janus project: Boosting spin-glass simulations using FPGAs

MAIORANO, Andrea;
2013-01-01

Abstract

Spin-glasses have become one of the most computing-demanding problems of the last 50 years in Statistical Physics. These extremely slow systems represent a clear example of an easy-to-describe but hard-to-simulate numerical problem. We have developed an FPGAs architecture, called Janus, able to exploit the simplicity of the problem by an extensive parallelization of the computing units. In this work we describe the architecture after motivating the problem. We give the performance figures compared with other more usual architectures. We have obtained a clear advantage in terms of computing power which produced several top results in the field. In addition, we describe the current development of the next generation of the infrastructure: Janus II. © IFAC.
2013
9783902823533
M., B.J., R. A., B.N., A., C., L. A., F., J. M., G.N., A., G.G., et al. (2013). The Janus project: Boosting spin-glass simulations using FPGAs. In Programmable Devices and Embedded Systems (pp.227-232). IFAC Secretariat [10.3182/20130925-3-cz-3023.00039].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11365/1126654