Design and Implementation of Two Hardware Silicon Prototypes for Cryptography and Hardware Security Applications

This thesis reports the main research results that I achieved during my PhD program at the Department of Information Engineering and Mathematics of the University of Siena, Italy. The purpose of my research was to study and design lightweight crypto-hardware silicon Integrated Circuits (ICs) based on non-linear dynamical systems for hardware security and cryptographic applications. The objectives of this work were ambitious, since the goal was facing the design of silicon True Random Bit Generators (TRBGs) and Physically Unclonable Functions (PUFs) with new methods and multidisciplinary approaches, linking together Measure Theory, Neural Networks, Complex Systems, Nonlinear Dynamics, Integrated Circuit design and technology, as well as Cryptography. This thesis is divided in two parts. The first part presents the study and the design of an IC implementing a chaos-based TRBG with statistical self-tuning capabilities. As a result of my research, an integrated circuit was designed and taped-out during my PhD program. The IC is a full custom mixed-signal circuit implementing a TRBG based on a discrete-time piecewise linear 1D chaotic map. The TRBG exploits self-tuning capabilities to achieve the maximum entropy, which is obtained monitoring and adjusting the chaotic map parameters to compensate possible perturbing deviances due to, e.g., technological process variability and temperature variations. To this aim, the IC is equipped with a digital core analyzing the statistical characteristics of the generated sequences, to achieve the estimation of the chaotic system parameters and to perform a digitized control and correction of the analog circuit implementing the map. The chip has been fabricated after being selected and ranked among the 10 best project proposals in the very first user category, in the second EUROPRACTICE First User Stimulation action. The IC has been fabricated at the end of April, 2018, and tested in June/July 2018. To house and power the IC a PCB has been designed and fabricated, providing the necessary physical analog and digital interfaces for the chip testing. Furthermore, the testing environment has been developed in the LABVIEW environment exploring to a development board equipped with a Xilinx FPGA, and providing the software and hardware tools to perform the tests. The second part of this thesis presents the study and the design of an IC implementing a novel PUF circuit derived from Cellular Neural Networks (CNNs). The fundamental idea in this research is to exploit the rich dynamical versatility of CNNs to derive a novel class of low-complexity mixed-signal silicon PUFs, taking advantages from a wide set of mathematical models that can be analyzed by means of well-established theoretical tools. Also for this research activity, as a result of my research, an integrated circuit was designed and taped-out during my PhD program. The design of the hardware silicon prototype aimed to study the feasibility of the proposal, referring to standard mixedsignal CMOS technologies, and exploring different architectures and circuit topologies. The chip database for the tape-out was delivered at the end of August 2019, and at the time of writing this thesis the chip was currently under fabrication. In both of the research activities the results were achieved through circuit simulations, including the effects of temperature variations and technological process variability to verify and refine the proposed theoretical models. The activities presented in this thesis covered the design of the proposed circuits both at the electrical and physical levels, including post-layout validation and the writing of the design documentation.