We investigate and compare three low complexitycircuit topologies to be implemented in programmable logicdevices, for the design of True Random Bit Generators forLightweight Cryptography. The architectures, based on thegeneral idea of Digital Nonlinear Oscillators (DNOs), have beencompared on the basis of measurement campaigns, carried outreferring to figures of merit specifically introduced to assess thequality and reliability of the oscillators under test.
Addabbo, T., Fort, A., Moretti, R., Mugnaini, M., Vignoli, V., Garcia-Bosque, M. (2019). Lightweight true random bit generators in PLDs: figures of merit and performance comparison. In Proceedings - IEEE International Symposium on Circuits and Systems. New York : Institute of Electrical and Electronics Engineers Inc. [10.1109/ISCAS.2019.8702791].
Lightweight true random bit generators in PLDs: figures of merit and performance comparison
Addabbo, T.;Fort, A.;Moretti, R.;Mugnaini, M.;Vignoli, V.;
2019-01-01
Abstract
We investigate and compare three low complexitycircuit topologies to be implemented in programmable logicdevices, for the design of True Random Bit Generators forLightweight Cryptography. The architectures, based on thegeneral idea of Digital Nonlinear Oscillators (DNOs), have beencompared on the basis of measurement campaigns, carried outreferring to figures of merit specifically introduced to assess thequality and reliability of the oscillators under test.
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https://hdl.handle.net/11365/1082824