The growing diffusion of heterogeneous Cyber-Physical Systems (CPSs) poses a problem of security. The employment of cryptographic strategies and techniques is a fundamental part in the attempt of finding a solution to it. Cryptographic algorithms, however, need to increase their security level due to the growing computational power in the hands of potential attackers. To avoid a consequent performance worsening and keep CPSs functioning and secure, these cryptographic techniques must be implemented so to exploit the aggregate computational power that modern parallel architectures provide. In this chapter we investigate the possibility to parallelize two very common basic operations in cryptography: modular exponentiation and Karatsuba multiplication. For the former, we propose two different techniques (m-ary and exponent slicing) that reduce calculation time of 30/40%. For the latter, we show various implementations of a 3-thread parallelization scheme that provide up to 60% better performance with respect to a sequential implementation.
Bartolini, S., Peccerillo, B. (2018). Parallel programming in cyber-physical systems. In Cyber-Physical Systems Security (pp. 111-134). Springer International Publishing [10.1007/978-3-319-98935-8_6].
Parallel programming in cyber-physical systems
Bartolini S.;Peccerillo B.
2018-01-01
Abstract
The growing diffusion of heterogeneous Cyber-Physical Systems (CPSs) poses a problem of security. The employment of cryptographic strategies and techniques is a fundamental part in the attempt of finding a solution to it. Cryptographic algorithms, however, need to increase their security level due to the growing computational power in the hands of potential attackers. To avoid a consequent performance worsening and keep CPSs functioning and secure, these cryptographic techniques must be implemented so to exploit the aggregate computational power that modern parallel architectures provide. In this chapter we investigate the possibility to parallelize two very common basic operations in cryptography: modular exponentiation and Karatsuba multiplication. For the former, we propose two different techniques (m-ary and exponent slicing) that reduce calculation time of 30/40%. For the latter, we show various implementations of a 3-thread parallelization scheme that provide up to 60% better performance with respect to a sequential implementation.File | Dimensione | Formato | |
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https://hdl.handle.net/11365/1083643