Bus Utilization Analysis of Multithreaded Shared-Bus Multiprocessors

A shared-bus shared-memory system based on multithreaded processors is evaluated against different solutions for cache, processor scheduling, and coherence protocols. Multithreaded architectures have been intensively studied for DSM multiprocessors, where latencies are a major factor in limiting performance, but may be interesting also for bus-based multiprocessors, since processor speed are increasing at a much faster rate than memory. In these systems, not only pure parallel workloads, but also general workloads (i.e. constituted of both parallel and sequential applications) are the typical object of user demand for computational power. On these machines, load balancing may easily cause process migration sharing. Taking in mind also that problem, the aim of this work is therefore to investigate the relations among this kind of workloads, multithreaded processors, shared-bus architecture and coherence schemes and thereby the consequences on performance.