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A comprehensive design flow, easy to automate with commercial CAD tools, is presented to optimize nanometer FFs under constraints within the E-D space. By referring to practical design cases, transistor sizing is addressed rigorously. Cases of study for FFs in a 65-nm technology are reported for validation.

Alioto, M.B.C., E., C., G., P. (2010). Nanometer Flip-Flops Design in the E-D Space. In Proc. of ICM 2010 (pp.132-135). New York : IEEE [10.1109/ICM.2010.5696091].

Nanometer Flip-Flops Design in the E-D Space

ALIOTO, MASSIMO BRUNO CRIS;
2010-01-01

Abstract

A comprehensive design flow, easy to automate with commercial CAD tools, is presented to optimize nanometer FFs under constraints within the E-D space. By referring to practical design cases, transistor sizing is addressed rigorously. Cases of study for FFs in a 65-nm technology are reported for validation.
2010
9781612841496
978-1-61284-151-9
Alioto, M.B.C., E., C., G., P. (2010). Nanometer Flip-Flops Design in the E-D Space. In Proc. of ICM 2010 (pp.132-135). New York : IEEE [10.1109/ICM.2010.5696091].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11365/36172
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