In this paper, issues related to the physical design and layout density of FinFET standard cells are discussed. Analysis significantly extends previous analyses, which considered the simplistic case of a single FinFET device or extremely simple circuits. Results show that analysis of a single device cannot predict the layout density of FinFET cells, due to the additional spacing constraints imposed by the standard cell structure. Results on the layout density of FinFET standard cell circuits are derived by building and analyzing various cell libraries in 32-nm technology, based on 3T and four-terminal (4T) devices, as well as on the recently proposed cells with mixed 3T-4T devices (MT). The results obtained for spacer- and lithography-defined FinFETs are observed from the technology scaling perspective by also considering 45-nm and 65-nm libraries. The effect of the fin and cell height on the layout density is studied. Results show that that 3T and MT FinFET standard cells can have the same layout density as bulk cells (or better) for low (moderate) fin heights. Instead, 4T standard cells have an unacceptably worse layout density. Hence, MT standard cells turn out to be the only viable option to apply back biasing in FinFET standard cell circuits.

Alioto, M.B.C. (2010). Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 19(5), 751-762 [10.1109/TVLSI.2010.2040094].

Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells

ALIOTO, MASSIMO BRUNO CRIS
2010-01-01

Abstract

In this paper, issues related to the physical design and layout density of FinFET standard cells are discussed. Analysis significantly extends previous analyses, which considered the simplistic case of a single FinFET device or extremely simple circuits. Results show that analysis of a single device cannot predict the layout density of FinFET cells, due to the additional spacing constraints imposed by the standard cell structure. Results on the layout density of FinFET standard cell circuits are derived by building and analyzing various cell libraries in 32-nm technology, based on 3T and four-terminal (4T) devices, as well as on the recently proposed cells with mixed 3T-4T devices (MT). The results obtained for spacer- and lithography-defined FinFETs are observed from the technology scaling perspective by also considering 45-nm and 65-nm libraries. The effect of the fin and cell height on the layout density is studied. Results show that that 3T and MT FinFET standard cells can have the same layout density as bulk cells (or better) for low (moderate) fin heights. Instead, 4T standard cells have an unacceptably worse layout density. Hence, MT standard cells turn out to be the only viable option to apply back biasing in FinFET standard cell circuits.
2010
Alioto, M.B.C. (2010). Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 19(5), 751-762 [10.1109/TVLSI.2010.2040094].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11365/34308
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