Abstract The design of new computer systems always requires a strong simulation effort in order to evaluate different design options. This is especially true if the system is to be produced at a date far in the future, such as in the case of TERAFLUX, a system aimed at containing something like 1012 (1 TERA) transistors in a single package or a (multilayer) chip by 2020. At the basis of a \TERAFLUX\ system, a dataflow execution model supports the execution of threads. In order to explore the design space, \TERAFLUX\ provides an appropriate evaluation framework, at the scale of at least 1000 general purpose cores on a single chip. Predicting the performance of such a next-generation platform is not a trivial task. Today, no software-based tool exists that can provide cycle-level full-system simulation and faithfully predict the behavior of 1000 general-purpose cores, in an acceptable amount of time and with reasonable accuracy, while providing the flexibility of changing the execution model at the architectural level. A solid evaluation framework represents an important base for exploring future many cores. In this chapter, different options for simulating a 1000 general-purpose-core system are explored. Finally, we show the setup that successfully allowed us to evaluate our 1000 core target while running a full-system Linux operating system.

Giorgi, R. (2017). Exploring future many-core architectures: the TERAFLUX evaluation framework. In Advances in Computers (pp. 33-72). Academic Press Inc. [10.1016/bs.adcom.2016.09.002].

Exploring future many-core architectures: the TERAFLUX evaluation framework

GIORGI, ROBERTO
Writing – Review & Editing
2017-01-01

Abstract

Abstract The design of new computer systems always requires a strong simulation effort in order to evaluate different design options. This is especially true if the system is to be produced at a date far in the future, such as in the case of TERAFLUX, a system aimed at containing something like 1012 (1 TERA) transistors in a single package or a (multilayer) chip by 2020. At the basis of a \TERAFLUX\ system, a dataflow execution model supports the execution of threads. In order to explore the design space, \TERAFLUX\ provides an appropriate evaluation framework, at the scale of at least 1000 general purpose cores on a single chip. Predicting the performance of such a next-generation platform is not a trivial task. Today, no software-based tool exists that can provide cycle-level full-system simulation and faithfully predict the behavior of 1000 general-purpose cores, in an acceptable amount of time and with reasonable accuracy, while providing the flexibility of changing the execution model at the architectural level. A solid evaluation framework represents an important base for exploring future many cores. In this chapter, different options for simulating a 1000 general-purpose-core system are explored. Finally, we show the setup that successfully allowed us to evaluate our 1000 core target while running a full-system Linux operating system.
2017
Giorgi, R. (2017). Exploring future many-core architectures: the TERAFLUX evaluation framework. In Advances in Computers (pp. 33-72). Academic Press Inc. [10.1016/bs.adcom.2016.09.002].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11365/1003141