Sfoglia per Autore
IRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor
2018-01-01 Zhang, Y.; Khayatzadeh, M.; Yang, K.; Saligane, M.; Pinckney, N.; Alioto, M.; Blaauw, D.; Sylvester, D.
Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm
2018-01-01 Taneja, S.; Alvarez, A. B.; Alioto, M.
Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm
2016-01-01 Alvarez, A. B.; Zhao, W.; Alioto, M.
Variations in nanometer CMOS flip-flops: Part i - Impact of process variations on timing
2015-01-01 Alioto, M.; Consoli, E.; Palumbo, G.
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study
2014-01-01 Wenfeng, Zhao; Yajun, Ha; Alioto, MASSIMO BRUNO CRIS
Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches
2014-01-01 Elio, Consoli; Gaetano, Palumbo; Jan M., Rabaey; Alioto, MASSIMO BRUNO CRIS
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations
2014-01-01 Alioto, MASSIMO BRUNO CRIS; Simone, Bongiovanni; Milena, Djukanovic; Giuseppe, Scotti; Alessandro, Trifiletti
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
2014-01-01 Fabio, Frustaci; Mahmood, Khayatzadeh; David, Blaauw; Dennis, Sylvester; Alioto, MASSIMO BRUNO CRIS
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)
2014-01-01 Alioto, MASSIMO BRUNO CRIS; Simone, Bongiovanni; Giuseppe, Scotti; Alessandro, Trifiletti
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I-Device-Circuit Interaction and Evaluation at Device Level
2014-01-01 David, Esseni; Manuel, Guglielmini; Bernard, Kapidani; Tommaso, Rollo; Alioto, MASSIMO BRUNO CRIS
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions
2013-01-01 Alioto, MASSIMO BRUNO CRIS; Elio, Consoli; Jan M., Rabaey
Enabling sizing for enhancing the static noise marginsInternational Symposium on Quality Electronic Design (ISQED)
2013-01-01 Valeriu, Beiu; Azam, Beg; Walid, Ibrahim; Fekri, Kharbash; Alioto, MASSIMO BRUNO CRIS
On upsizing length and noise marginsCAS 2013 (International Semiconductor Conference)
2013-01-01 Valeriu, Beiu; Mihai, Tache; Walid, Ibrahim; Fekri, Kharbash; Alioto, MASSIMO BRUNO CRIS
45pW ESD clamp circuit for ultra-low power applicationsProceedings of the IEEE 2013 Custom Integrated Circuits Conference
2013-01-01 Yen Po, Chen; Yoonmyung, Lee; Jae Yoon, Sim; Alioto, MASSIMO BRUNO CRIS; David, Blaauw; Dennis, Sylvester
Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits
2013-01-01 Felice, Crupi; Domenico, Albano; Alioto, MASSIMO BRUNO CRIS; Jacopo, Franco; Luca, Selmi; Jérôme, Mitard; Guido, Groeseneken
Design in the Energy-Delay Space
2012-01-01 Alioto, MASSIMO BRUNO CRIS; E., Consoli; G., Palumbo
Conditional Push-Pull Pulsed Latch with 726 fJ•ps Energy Delay Product in 65nm CMOS
2012-01-01 E., Consoli; Alioto, MASSIMO BRUNO CRIS; G., Palumbo; J., Rabaey
A Simple Keeper Topology to Reduce Delay Variations in Nanometer Domino Logic
2012-01-01 Alioto, MASSIMO BRUNO CRIS; G., Palumbo; M., Pennisi
Buried Silicon Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits under Aggressive Voltage Scaling
2012-01-01 F., Crupi; Alioto, MASSIMO BRUNO CRIS; J., Franco; P., Magnone; B., Kaczer; G., Groeseneken; J., Mitard; L., Witters; T. Y., Hoffmann
Mixed FBB/RBB: a Novel Low-Leakage Technique for FinFET Forced Stacks
2012-01-01 D., Baccarin; D., Esseni; Alioto, MASSIMO BRUNO CRIS
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