Sfoglia per Autore KHALILI MAYBODI, FARNAM
Mostrati risultati da 1 a 7 di 7
A Dynamic Load Balancer for a Cluster of FPGA SoCs
2020-01-01 KHALILI MAYBODI, Farnam; Giorgi, Roberto
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise: Designing a Computer Architecture via HLS)
2019-01-01 Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco
A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface
2019-01-01 KHALILI MAYBODI, Farnam; Giorgi, Roberto
An FPGA-based Scalable Hardware Scheduler for Data-Flow Models
2018-01-01 Procaccini, Marco; KHALILI MAYBODI, Farnam; Giorgi, Roberto
Reconfigurable Logic Interface Architecture for CPU-FPGA Accelerators
2018-01-01 KHALILI MAYBODI, Farnam; Giorgi, Roberto; Procaccini, Marco
Energy Efficiency Exploration on the ZYNQ Ultrascale+
2018-01-01 Giorgi, Roberto; Khalili, Farnam; Procaccini, Marco
From COTSon to HLS: translating timing into an architecture
2018-01-01 Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco
| Titolo | Data di pubblicazione | Autore(i) | File | Abstract |
|---|---|---|---|---|
| A Dynamic Load Balancer for a Cluster of FPGA SoCs | 1-gen-2020 | KHALILI MAYBODI, Farnam; Giorgi, Roberto | - | |
| Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise: Designing a Computer Architecture via HLS) | 1-gen-2019 | Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco | - | |
| A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface | 1-gen-2019 | KHALILI MAYBODI, Farnam; Giorgi, Roberto | - | |
| An FPGA-based Scalable Hardware Scheduler for Data-Flow Models | 1-gen-2018 | Procaccini, Marco; KHALILI MAYBODI, Farnam; Giorgi, Roberto | - | |
| Reconfigurable Logic Interface Architecture for CPU-FPGA Accelerators | 1-gen-2018 | KHALILI MAYBODI, Farnam; Giorgi, Roberto; Procaccini, Marco | - | |
| Energy Efficiency Exploration on the ZYNQ Ultrascale+ | 1-gen-2018 | Giorgi, Roberto; Khalili, Farnam; Procaccini, Marco | - | |
| From COTSon to HLS: translating timing into an architecture | 1-gen-2018 | Giorgi, Roberto; KHALILI MAYBODI, Farnam; Procaccini, Marco | - |
Mostrati risultati da 1 a 7 di 7
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